With its talented team of engineers and close links to high quality academic institutions, NanoZeta is committed to the pioneering of technological advances in Analog and RF device modeling, circuit design and system architectures.

Nano-Zeta continuously invests in IP development to remain in the vanguard of the next generation, high frequency wireless product suppliers.


Core Competencies

Nanozeta's Core Team


Senior AMS / RF IC Design Engineer

  • Education: BSc in Physics, PhD in Electronics

  • Businesss Experience: 15 years in Analog/RF/MS IC Design

  • Works and Publications: Participated in projects developing a DDR2/3 PHY, a USB3 PHY, a 60GHz PLL, a great number of low jitter fractional-N/Integer PLLs, de-skewing PLLs and Spread Spectrum Clock generators. Full design flow of analog blocks (OpAmps, BGRs, CPs, VCOs, drivers) and RF Blocks (LNAs Mixers etc). Evaluating IC processes in 28fdsoi, 40nm, 65nm.

  • Author/coAuthor of 35+ publications in high level journals and conferences. Co-inventor of 2 patents.


Senior Analog / RF Design Engineer

  • Education: BSc and MEng in Electrical and Computer Engineering

  • Business Experience: 10 years in RF/Analog/MS IC design

  • Works and Publications: Participated in projects developing PLL/VCOs for various applications, among which 60GHz PLLs with LC VCOs, USB3 clocking PLL with ring oscillator, Wifi/Bluetooth/BLE PLLs. Also designed RF amplifiers and worked extensively with full design and verification flow of various electronics blocks.

  • Author or co-author of a number of conference papers.


Senior Analog / RF Design Engineer

  • Education: BSc in Physics, MSc in Electronics, PhD in Electronics

  • Business Experience: 6+ years in Analog/RF/MS IC Design

  • Works and Publications: Bandgap Reference, temperature sensor, class-AB amplifier, buck converter power stage, evaluation/characterization of devices for switching applications. Mixed-signal circuits for power management applications (series linearregulator, POR, Switched-Cap blocks, comparators, OTAs). Mixed-signal circuits for 5Gb/s serial data communication interfaces(Equalizer-TX/RX, DFE, CML Output Driver, CML Buffer, Latch, MUX,DFF,Phase Interpolator). Digital-assisted DC offset cancellation loop. Fully-balanced OTA-C 7th-order 100MHz Elliptic lowpass filter for Powerline AFE. 300MHz, 60dB-linear PGA with 1.4dB step for Powerline AFE

  • Author/Co-author of 18 papers in refereed international journals and conferences.


Senior Digital IC Design Engineer

  • Education: BSc in Physics, MSc in Microelectronics

  • Business Experience: 8+ years in Digital/Mixed signal IC Design

  • Works and Publications: RTL design and verification of complex digital systems for CMOS imaging applications using a variety of EDA tools. Worked on several projects (cameras, photonic sensors, auto-focus devices) from specification to tape-out in cooperation with major customers. Design and verification of complex digital and mixed-signal ASICs (USB3.0 PHY, DDR2/3 PHY) using a variety of EDA tools. Responsibilities include system design/specification, full RTL-to-GDSII flow with sign-off verification at each step, semi-custom layout using signal integrity aware highspeed techniques,technical documentation.

  • Author or co-author of 2 publications in high level journals and 2 conference papers.


Senior Analog / RF IC Design Engineer

  • Education: BSc in Physics, MSc in Electronics, PhD in Electronics

  • Business Experience: 15 years in Analog/RF/MS IC Design

  • Works and Publications: Participated in projects developing a USB3 and a 60GHz PLL system. Design of high-speed parts, drivers, etc. Evaluating IC process in 65nm. Full design flow of analog blocks (OpAmps, BGRs, Sampling latches, Phase interpolator, drivers). Full design flow of CML high speed blocks and paths in transmitters/receivers.

  • Design of integrated filters for broadband communication. Design of special high-speed (40Gb/s) electronic ICs for optical network applications (serializer part)

  • Author/co-author of 21 publications in high level journals and 9 conference papers. Co-inventor of 1 patent.


Mid-level Analog IC Design Engineer

  • Education: BSc in Physics, MSc in Electronics

  • Business Experience: 4+ years in Analog/RF/MS IC Design

  • Works and Publications: Analog/RF IC and physical design using EDA tools. Electrical Design, Physical Design and Verification of a USB2.0 UTMI transceiver. Design of a wideband (65MHz to 3GHz) LNA for ITU-T G.hn (G.9960 and G.9964) applications with variable gain, low noise figure and high linearity. Design of a 1GHz Low-Voltage Differential Signaling driver/receiver. Design a 6-bit flash ADC at 1.7, 2.5, and 5GHz sampling rates, implementaing in 1.2V using a new offset calibration technique.

  • Author or co-author of 2 conference papers.


Senior Technical Advisor

  • Education: Dipl. Eng., MSEE, Dr. Eng.

  • Business Experience: Over 30 years in analog and RF IC design.

  • Works and Publications: Design of analog and RF integrated circuits for telecommunication applications. Design of microelectronic circuits for radio transceivers in nm-scale CMOS and SiGe technologies. Design and development of CAD tools for microelectronic applications. Integrated inductor modeling and design. Modeling of the MOS transistor for HF applications. Design and modeling of passive microwave components on silicon substrates. Design of RFICs for operation beyond 60 GHz. Design of Front-End Modules in SiGe for 5G applications (sub-6 GHz / 28 GHz / 39 GHz). Example designs/products: A Cartesian Feedback Loop linearizer transmitter IC for TETRA applications, designed for a world leading telecom industry, SiGe integrated transceivers for 802.11 a/b/g/j, SiGe integrated transceivers for WiMAX, Wireless HDMI RFICs: a 5-6GHz (4x5) MIMO transmitter and receiver solution supporting up to 3Gbps of video transmission, compatible with draft 802.11n in 0.18um SiGe BiCMOS – employed in commercial products of leading consumer electronics firms, 40 GHz IF transceiver for Point to Point and backhaul application, implemented in 0.18um SiGe process for a major wireless backhaul customer, 40 GHz IF transceiver for backhaul and PtP applications implemented in 0.18um SiGe for a major PtP and wireless backhaul customer, 60 GHz RF/IF transceiver for point to point and backhaul application implemented in 90nm CMOS process including proprietary microwave passive components, 6 to 44 GHz full RF/IF transceiver ICs for backhaul and PtP applications implemented in 0.13um BiCMOS for a major PtP and wireless backhaul customer.

  • Author/coAuthor of 70+ publications mostly in IEEE Journals and Conferences. Co-inventor of 8 patents.


Project Manager

  • Education: PhD in Computer Science, MSc in Computer Science, BEng in Computer and Communications Engineering, Introduction to Project Management with PMI® Methodology

  • Business Experience: 8 years in Algorithm Design, 6 years in Project Management.

  • Works and Publications: Development, demonstration and evaluation of algorithms for positioning and horizontal handover, energy efficiency in heterogeneous access networks, shared access terrestrial-satellite backhauling; Specification of business-driven use cases, derivation of functional and non-functional requirements, architecture design, technical specifications, demonstration, and test-bed evaluation; Project management, business modeling, exploitation, product management, business development, rollout roadmap.

  • Authored and published more than 20 research papers in international scientific journals, proceedings of peer-reviewed conferences and workshops.