We have outsourced Design and Validation work to NanoZetaTech since November 2015
NanoZetaTech was responsible for the following tasks:
- Design and Layout of a low jitter baseband pll for system clock generation up to 350 MHz
- A DRC and LVS clean block has been delivered, including design documentation.
- The design was a combination of analog (schematics) and digital blocks (HDL).
- Validation of the PLL. A report has been delivered with all the measurement results.
- NanoZeta has proven to be a reliable partner for our organization and is very committed to deliver on time and with good quality
NanoZeta is very cooperative in finding optimal solutions in the interest of our organization and our customers and, if we have a resource shortage in the future, we are certainly considering to outsource new design activities to NanoZetaTech